![[Steve Friedl Logo]](/images/unixwiz-logo-140x80.gif){kind=logo}
This site uses advanced css techniques
The dgmon — diagnostic monitor — is booted from the hard drive from firmware mode, and each kind of hardware has its own set of tests. These are known as "Phases", and from the dgmon prompt the tests can be shown with LIST {board}.
There are others besides this, but we've not been able to capture the listings from our own system.
Getting into the diagnostic monitor involves booting into the program /dgmon from the first firmware prompt, and this loads from the hard drive. If the hard drive is failing, there won't be any chance at diagnostics.
PHASE # PHASE TYPE PHASE DESCRIPTION ======== ========== ================= 1 NORMAL Central Processor Unit Test #2 DGN 2 NORMAL Central Processor Unit Test #3 DGN 3 NORMAL Central Processor Unit Test #4 DGN 4 NORMAL Dynamic Random Access Memory DGN 5 DEMAND Extended DRAM Memory DGN 6 NORMAL Memory Management Unit Test #1 DGN 7 NORMAL Memory Management Unit Test #2 DGN 8 NORMAL Memory Management Unit Test #3 DGN 9 NORMAL Memory Management Unit Test #4 DGN 10 INTERACTIVE Non-Volatile Random Access Memory DGN 11 NORMAL Interrupt System DGN 12 NORMAL Sanity/Interval Timer DGN 13 NORMAL Control Status Register DGN 14 INTERACTIVE Dual UART DGN 15 INTERACTIVE Extended Dual UART DGN 16 INTERACTIVE Dual UART/Keyboard DGN 17 INTERACTIVE Time-of-Day Clock DGN 18 NORMAL Direct Memory Access Controller DGN 19 INTERACTIVE Floppy Disk Interface DGN 20 INTERACTIVE Extended Floppy Disk Interface DGN 21 NORMAL Physical MMU Cache DGN 22 DEMAND Extended Physical MMU Cache DGN 23 NORMAL Central Processor Unit Test #5 DGN 24 NORMAL Central Processor Unit Test #6 DGN 25 NORMAL Central Processor Unit Test #7 DGN 26 NORMAL Central Processor Unit Test #8 DGN
PHASE # PHASE TYPE PHASE DESCRIPTION ======== ========== ================= 1 NORMAL Math Accelerator #1 DGN 2 NORMAL Math Accelerator #2 DGN 3 NORMAL Math Accelerator #3 DGN 4 NORMAL Math Accelerator #4 DGN
PHASE # PHASE TYPE PHASE DESCRIPTION ======== ========== ================= 1 DEMAND SCSI CIO Sanity 2 DEMAND SCSI Upper RAM Write/Read 3 DEMAND SCSI Lower RAM Write/Read 4 DEMAND SCSI ROM Checksum 5 DEMAND SCSI CPU Upper Chip Select 6 DEMAND SCSI CPU DMA Internal 7 DEMAND SCSI CPU Timer 8 DEMAND SCSI CPU Interrupt Controller 9 DEMAND SCSI CPU Lower Chip Select 10 DEMAND SCSI PIO Byte Transfer 11 DEMAND SCSI PIO Word Transfer 12 DEMAND SCSI DMA Byte Transfer 13 DEMAND SCSI DMA Word Transfer 14 DEMAND SCSI FIFO 15 DEMAND SCSI External DMA Word 16 DEMAND SCSI Controller 17 DEMAND SCSI Reset Test 18 DEMAND SCSI Controller Buffer Test 19 DEMAND SCSI Controller Self Test 20 DEMAND SCSI Controller/Media Self Test 21 INTERACTIVE SCSI Interactive Tape Test 22 DEMAND SCSI Disk Write/Read Test 23 INTERACTIVE SCSI Interactive Disk Write/Read 24 NORMAL SCSI Configuration Status
The most common phases are #17 and #24. Phase #17 resets the SCSI bus and re-reads the list of attached devices, and is the only way we know of to get the system to recognize a new device short of rebooting. Phase #24 shows the list of all attached devices (but this is also included in a #17).
DGMON > dgn scsi ph=17
<<< DIAGNOSTIC MODE >>>
Phase # 17
Test: SCSI Reset Test
Tests : 4 Time : 60 seconds
Configuration:
ID# 0 Host Adapter
ID# 1 Disk Controller LU0
ID# 2 Tape Controller LU0
ID# 3 Tape Controller LU0
ID# 6 Tape Controller LU0
*** PHASE - ATP ***
SCSI 0 (IN I/O BUS SLOT 1) DIAGNOSTICS PASSED
DGMON >
PHASE # PHASE TYPE PHASE DESCRIPTION ======== ========== ================= 1 NORMAL PORTS - CIO & Peripheral Sanity 2 DEMAND PORTS - PCSR Read/Write 3 DEMAND PORTS - Upper RAM Verification 4 DEMAND PORTS - Lower RAM Verification 5 DEMAND PORTS - ROM Checksum 6 DEMAND PORTS - Upper Chip Select Registers 7 DEMAND PORTS - DMA Control Registers 8 DEMAND PORTS - CPU Writable Registers 9 DEMAND PORTS - Interrupt Control Registers 10 DEMAND PORTS - Lower Chip Select Register 11 DEMAND PORTS - PIO Byte Transfers 12 DEMAND PORTS - PIO Word Transfers 13 DEMAND PORTS - DMA Byte Transfer 14 DEMAND PORTS - DMA Word Transfer 15 INTERACTIVE PORTS - Printer Data Register 16 INTERACTIVE PORTS - Printer CSR Register 17 DEMAND PORTS - Duart 0 Internal Loop 18 DEMAND PORTS - Duart 1 Internal Loop 19 INTERACTIVE PORTS - Duart 0 External Loop 20 INTERACTIVE PORTS - Duart 1 External Loop 21 NORMAL PORTS - Duart 0 Loop Sanity 22 NORMAL PORTS - Duart 1 Loop Sanity
PHASE # PHASE TYPE PHASE DESCRIPTION ======== ========== ================= 1 NORMAL EPORTS - CIO & Peripheral Sanity 2 DEMAND EPORTS - Upper RAM Verification 3 DEMAND EPORTS - Lower RAM Verification 4 DEMAND EPORTS - ROM Checksum 5 DEMAND EPORTS - Upper Chip Select Registers 6 DEMAND EPORTS - DMA Control Registers 7 DEMAND EPORTS - CPU Writable Registers 8 DEMAND EPORTS - Interrupt Control Registers 9 DEMAND EPORTS - Lower Chip Select Register 10 DEMAND EPORTS - PIO Byte Transfers 11 DEMAND EPORTS - PIO Word Transfers 12 DEMAND EPORTS - DMA Byte Transfer 13 DEMAND EPORTS - DMA Word Transfer 14 DEMAND EPORTS - SCC Basic Sanity 15 DEMAND EPORTS - DTR & Basic Interrupt Integrity 16 DEMAND EPORTS - SCC Receive Buffers 17 DEMAND EPORTS - Basic DMAC & SCC Test 18 DEMAND EPORTS - Local SCC Interrupts 19 INTERACTIVE EPORTS - External SCC Interrupts 20 INTERACTIVE EPORTS - External Drivers & Receivers 21 DEMAND EPORTS - Complete DMAC & SCC Test
PHASE # PHASE TYPE PHASE DESCRIPTION ======== ========== ================= 1 NORMAL Phase #01 - CIO Sanity Test 2 DEMAND Phase #02 - PCSR Write/Read Test 3 DEMAND Phase #03 - Upper RAM Write/Read Test 4 DEMAND Phase #04 - Lower RAM Write/Read Test 5 DEMAND Phase #05 - ROM Checksum Test 6 DEMAND Phase #06 - CPU Chip Select Test 7 DEMAND Phase #07 - CPU DMA Internal Test 8 DEMAND Phase #08 - CPU Timer Test 9 DEMAND Phase #09 - CPU Interrupt Controller 10 DEMAND Phase #10 - CPU Lower Chip Select Test 11 DEMAND Phase #11 - Programmed I/O Byte 12 DEMAND Phase #12 - Programmed I/O Word 13 DEMAND Phase #13 - DMA Transfer Byte Test 14 DEMAND Phase #14 - DMA Transfer Word Test 15 DEMAND Phase #15 - NI Internal Loop (82586) 16 DEMAND Phase #16 - NI Internal Loop (82586) 17 DEMAND Phase #17 - NI External Loop (82501) 18 NORMAL Phase #18 - NI External Loop (XCVR) 19 DEMAND Phase #19 - Time Domain Reflectometer
DIAGNOSTIC PHASE TABLE FOR CTC PHASE # PHASE TYPE PHASE DESCRIPTION ======== ========== ================= 1 NORMAL Phase #01 - CIO Sanity Test 2 DEMAND Phase #02 - PCSR Write/Read Test 3 DEMAND Phase #03 - Upper RAM Write/Read Test 4 DEMAND Phase #04 - Lower RAM Write/Read Test 5 DEMAND Phase #05 - ROM Checksum Test 6 DEMAND Phase #06 - CPU Chip Select Test 7 DEMAND Phase #07 - CPU DMA Internal Test 8 DEMAND Phase #08 - CPU Timer Test 9 DEMAND Phase #09 - CPU Interrupt Controller 10 DEMAND Phase #10 - CPU Lower Chip Select Test 11 DEMAND Phase #11 - Programmed I/O Byte 12 DEMAND Phase #12 - Programmed I/O Word 13 DEMAND Phase #13 - DMA Transfer Byte Test 14 DEMAND Phase #14 - DMA Transfer Word Test 15 NORMAL Phase #15 - CTC/DMAC Register Test 16 INTERACTIVE Phase #16 - CTC Tape/DMAC Test 17 INTERACTIVE Phase #17 - CTC Floppy/DMAC Test 18 INTERACTIVE Phase #18 - Fast CTC Tape/DMAC Test
![[Steve's Email]](/images/steve-email.gif)